A non-volatile memory cell retains information stored in the memory cell even when the power is turned off. To create a non-volatile memory cell, typically a standard CMOS-based logic process is used as a starting foundation. Next, additional process steps are incorporated into the logic process flow to create the non-volatile memory cell. Examples of such additional process steps include second polysilicon deposition, junction dopant optimization, etc. Integrating “non-volatile memory”-specific process steps into the standard CMOS-based logic process creates complications. Consequently, embedded non-volatile memory technologies generally lag behind advanced logic fabrication processes by several generations. For a system-on-chip (SoC) approach, which requires embedding a non-volatile memory, a design team may have no choice but to accept a logic flow process usually two to three generations behind the current advanced standard logic process as well as the addition to that process of seven to eight additional lithographic masks. This prior approach not only typically increases the wafer cost, but it also falls short of the peak performance that the most advanced standard logic process can deliver.
Also, due to the cycling-induced degradation of the SiO2, the previous technique of subjecting all of the non-volatile memory cell components to the higher program and erase voltages typically hastens the degradation of the SiO2, thus degrading the performance and reliability of the non-volatile memory cell.
Structures and fabrication methods have therefore been explored to solve the above-discussed problems. U.S. Pat. No. 6,788,574 discusses a non-volatile memory cell 400. A top view is illustrated in FIG. 1. The non-volatile memory cell 400 consists of a tunneling capacitor 406, a coupling capacitor 402 and a read transistor 404. These three components share a single floating gate 408. The plates of the coupling capacitor 402 and the tunneling capacitor 406 that are opposite the floating gate 408 are formed by connecting respective source/drain regions of MOS devices. The transistor 404 uses the floating gate 408 as the gate electrode. The coupling capacitor 402, in conjunction with the tunneling capacitor 406, forms the charging component, which is operable to facilitate programming and erasing of information stored in the non-volatile memory cell 400. Thus, a program/erase operation enables retention of information after the power is turned off, while a read operation allows the previously stored information to be accessed after powering the memory back up. During a read operation, the information is detected using the read transistor 404.
In one embodiment, the program and erase operations of the non-volatile memory cell are achieved by tunneling electrons into and out of the floating gate 408 through the tunneling capacitor 406 to alter the charge state of the memory cell. For example, to program the non-volatile memory cell 400, a positive voltage is applied to a node 410 while a node 412 is grounded. Due to the capacitive coupling of the coupling capacitor 402 and the tunneling capacitor 406, a large voltage drop is produced across the tunneling capacitor 406, resulting in a high electric field between its two plates. When the electrical field is sufficiently high for Fowler Nordheim tunneling to occur, electrons from the active region 414 can tunnel through the insulating material between the floating gate 408 and the underlying active regions 414, and inject into the floating gate 408.
Conversely, by applying a positive voltage to the node 412 and grounding the node 410, electrons in the floating gate 408 can tunnel out of the floating gate 408, and thus the negative charge in the floating gate is reduced.
The non-volatile memory cell 400 shown in FIG. 1 suffers drawbacks, however. The memory cell is not isolated from other cells in the same memory array, thus memory cells in the same memory array affect each other. If a memory cell is at a state where the transistor 404 is on, during a read operation of other memory cells in the same memory array, current still flows through the transistor 404. For the memory array, this current is undesirable and considered to be a leakage current. With multiple cells in a memory array, the leakage current may be significant. To reduce the leakage current, it is preferred for each of the memory cells to comprise a logic circuit to control its operation. As a result, the total chip area for the memory cell and the logic circuit increases. Typically, the total area may be as great as 500 μm2. Additionally, during the program and erase operations, electrons all tunnel through the same tunneling capacitor 406. This not only affects the reliability of the memory cell, but it also increases the chances of over-programming and/or over-erasing.
What is needed, therefore, is an improved non-volatile memory cell having reduced leakage current and requiring less chip area.